During the manufacturing of many semiconductor devices, trenches are formed in a layer of material, and then the trenches are filled. For instance, trenches may be formed in the inter-layer dielectric (ILD), and those trenches may be filled with copper, thereby forming interconnect lines along the trenches.
During manufacturing, a continuous hardmask layer is added on top of the ILD, and a patterned resist layer is formed over selected portions of the hardmask. Trenches are then etched through openings in the resist layer. The etching step causes both the exposed hardmask and exposed ILD to be etched, thereby forming a trench in the ILD. However, the ILD is typically more susceptible to etching than the hardmask. This is because ILD often made of a very low-K (e.g., K being 2.5 or less) porous material. Because of this, the trench is formed to be wider at its mouth than the corresponding opening in the hardmask, thereby forming an undercut under the hardmask. Such undercuts can reduce interconnect reliability in the finished product due to increased electro-migration and stress migration problems. This undercut problem has hindered manufacturers from forming interconnects in very low-K ILDs.
Some manufacturers have attempted to avoid this problem by not using a hardmask over the ILD. However, there are problems with not using a hardmask, such as moisture absorption that affects the capacitances between various circuit elements in an unpredictable and undesirable manner.